1. Field
Exemplary embodiments of the present invention relate to a memory device.
2. Description of the Related Art
Memory devices may include a plurality of memory cells, each of which includes a cell transistor serving as a switch and a cell capacitor for storing a charge (data). Data of a memory cell may be determined as ‘high’ (logic 1) or ‘low’ (logic 0) depending on the charge stored in the cell capacitor of the memory cell, that is, whether a terminal voltage of the cell capacitor is high or low.
In principle, maintaining data stored in a memory cell as an accumulated charge in a cell capacitor, requires no power consumption. However, in practice, an initial charge stored in a cell capacitor may degrade overtime due to a leakage current caused, for example, near a PN junction of a MOS transistor, which in turn may cause a data loss. Furthermore, as the degree of integration of memory devices continues to increase and the width of line patterns (or critical dimension) decreases, the capacitance of a cell capacitor is reduced as compared with the capacitance of a bit line capacitor, so that a voltage difference for distinguishing data stored in the memory cell becomes smaller. As a result, there is an increased likelihood that a 1-bit failure occurs. Such 1-bit failure is commonly referred to as an intermittent tWR failure (hereinafter, also referred to as an intermittent failure).
An intermittent failure does not occur continuously in a specific cell but may occur rather irregularly, hence addressing such a failure may be problematic.
For example, a memory device such as a DRAM may perform a typical refresh operation on a constant cycle. Since an intermittent failure may occur during a refresh operation, it is difficult to prevent an intermittent failure through a typical refresh operation. Furthermore, even though a failed cell detected through a test in a production stage of a memory device may be repaired with a redundancy cell, it may be difficult to prevent an intermittent failure through conventional test and repair since an intermittent failure may also occur in a memory cell which is not detected as a failed cell.